FINAL PROGRAM
2nd Workshop on Architectural and Microarchitectural Support for Binary Translation
Held in conjunction with the 36th Int'l Symposium on Computer Architecture (ISCA-36)
Austin, Texas -- June 20, 2009
http://amas-bt.cs.virginia.edu/
The AMAS-BT organizing and program committee would like to invite you to attend the Workshop on Architectural and MicroArchitectural Support for Binary Translation to be held in Austin, Texas on June 20, 2009, in conjunction with the 36th International Symposium on Computer Architecture (ISCA).
This workshop will feature a keynote by Antonio Gonzalez, Director, Intel Barcelona Research Center on "Hardware-Software Co-Designed Processors" and four technical papers. Please see the advance program below.
8:30 AM - Opening and Keynote
- Hardware/Software Co-Designed Processors
Antonio Gonzalez, Director, Intel Barcelona Research Center, Intel Corporation
[Abstract]
9:30 AM - Session 1
- Detecting Self-Modifying Code
David Keppel, Google
[Paper] [Presentation]
10:00 AM - Break
10:30 AM - Session 2
- Compact Trace Trees in Dynamic Binary Translation
Joao Paulo Porto, Guido Araujo, UNICAMP, Youfeng Wu, Edson Borin, Cheng Wang, Intel Corporation
[Paper] [Presentation] - Transmeta Crusoe: Hardware, Software and Development
David Keppel, Google
[Paper] [Presentation] - Requirements for Fast Binary Translation
Mathias Payer and Thomas Gross, ETH, Zurich
[Paper] [Presentation]